| 发明名称 |
DELAY CIRCUIT AND DIGITAL TO TIME CONVERTER |
| 摘要 |
A delay circuit includes a first inverter in which a delay time of rising is larger than a delay time of falling, and a second inverter which is connected in series with the first inverter and in which a delay time of falling is larger than a delay time of rising. Transistors for each of the first and second inverters are connected in series between a power supply terminal and a ground terminal. |
| 申请公布号 |
US2015035690(A1) |
申请公布日期 |
2015.02.05 |
| 申请号 |
US201414191297 |
申请日期 |
2014.02.26 |
| 申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
MIYASHITA Daisuke |
| 分类号 |
H03K5/13;H03M1/82 |
主分类号 |
H03K5/13 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A delay circuit comprising:
a first inverter in which a delay time of rising is larger than a delay time of falling; and a second inverter which is connected in series with the first inverter, and in which a delay time of falling is larger than a delay time of rising, wherein transistors for each of the first inverter and the second inverter are connected in series between a first power terminal and a second power terminal. |
| 地址 |
Tokyo JP |
