FFMA OPERATIONS USING A MULTI-STEP APPROACH TO DATA SHIFTING

摘要

A fused floating-point multiply-add element includes a multiplier that generates a product, and a shifter that shifts an addend within a narrow range. Interpreting logic analyzes the magnitude of the addend relative to the product and then causes logic arrays to position the shifted addend within the left, center, or right portions of a composite register depending in the magnitude of the addend relative to the product. The interpreting logic also forces other portions of the composite register to zero. When the addend is zero, the interpreting logic forces all portions of the composite register to zero. Final combining logic then adds the contents of the composite register to the product.

主权项

1. A computer-implemented method for performing an arithmetic operation, the method comprising:
receiving a mantissa associated with a first operand; shifting the first mantissa to generate a first sequence of bits; storing the first sequence of bits in a first portion of a composite register; storing zeroes in one or more remaining portions of the composite register to generate a composite value; combining the composite value with the product of a second operand and a third operand to generate a final value.