发明名称 |
SIGNAL CONTROL CIRCUIT, INFORMATION PROCESSING DEVICE AND DUTY CALCULATION METHOD |
摘要 |
PROBLEM TO BE SOLVED: To provide a signal control circuit which facilitates segmentation of a factor in data abnormality, an information processing device and a duty calculation method.SOLUTION: A rise-side phase determination circuit 11 and a fall-side phase determination circuit 12 in a memory interface circuit 1 calculate a first delay amount to be added to an input signal for adjusting timing of rise of the input signal and rise or fall of a reference signal and a second delay amount to be added to the input signal for adjusting timing of fall of the input signal and fall or rise of the reference signal. A duty calculation part 14 calculates a duty of the input signal on the basis of a difference between the first delay amount and the second delay amount. |
申请公布号 |
JP2015026295(A) |
申请公布日期 |
2015.02.05 |
申请号 |
JP20130156135 |
申请日期 |
2013.07.26 |
申请人 |
FUJITSU LTD |
发明人 |
OKUBO KATSUHIKO;HASHIMOTO MICHITAKA;TOKUHIRO NORIYUKI |
分类号 |
G06F12/00;G06F1/04;G11C11/407;G11C11/4076 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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