| 摘要 |
A reduction operation device (6) detects a non-correspondence of an operation type or a data type in a reduction arithmetic operation during parallel processing. The reduction operation device (6) receives a plurality of synchronization signals and data, sets each transmission destination of the plurality of inputted synchronization signals and the plurality of data corresponding to a next stage of a reduction operation, and executes the reduction operation. A synchronization unit (8) in the reduction operation device (6) detects the non-correspondence between the operation type or the data type included in an instruction of the reduction operation after the synchronization is established and controls the arithmetic operation of an arithmetic unit (75). |
