| 摘要 |
Trailing (TZC) or leading zero counter 1100 comprises hardware logic blocks 1101 1104, each generating one bit of an output value (i.e. the number of trailing/leading zeros). Each block comprises two blocks 304, 306 of section logic to receive a section of an input string. Combining logic 308 then combines the outputs of section logic to generate the bit of the output value. Blocks 1102 1104 calculate bits other than the least significant bit of the output and comprise OR reduction stages 302 in series for reducing the length of the input string by pairwise combining of bits using OR gates before the resultant string is divided into two sections and input to the section hardware logic. The input string can be recursively split in sections of different lengths. Advantages include matching the timing profile of a preceding logic, e.g. section bits arriving first can be processed ahead of later arriving bits. |
