Via structure for integrated circuits

摘要

An integrated circuit (IC) having a concentric arrangement of stacked vias is disclosed. The IC includes first and second pluralities of signal lines on first and second metal layers, respectively. The second metal layer is arranged between the first metal layer and a silicon layer. The IC also includes a via structure implemented in a predefined area, and connects each of the first and second pluralities of signal lines to circuitry in the silicon layer through respective first and second pluralities of vias. Each via of the first and second pluralities has a center point that extends along a vertical axis from its respective metal layer to the silicon layer. Centers of each of the second plurality of vias are closer to a perimeter of the predefined area than respective centers of any of the first plurality of vias.

主权项

1. An integrated circuit comprising:
a first plurality of signal lines on a first metal layer; a second plurality of signal lines on a second metal layer, wherein the second metal layer is arranged between the first metal layer and a silicon layer, wherein each of the first plurality of signal lines has a greater vertical thickness than each of the second plurality of signal lines; a first via structure implemented in a first predefined area, the via structure connecting each of the first plurality of signal lines and each of the second plurality of signal lines to circuitry in the silicon layer, and wherein the first via structure includes:
a first plurality of vias each coupled to a corresponding one of the first plurality of signal lines and further coupled to circuitry in the silicon layer, wherein a center of each of the first plurality of vias extends along a vertical axis between the first metal layer and the silicon layer; anda second plurality of vias each coupled to a corresponding one of the second plurality of signal lines and further coupled to circuitry in the silicon layer, wherein a center of each of the second plurality of vias extends along the vertical axis between the second metal layer and the silicon layer, and wherein the center of each of the second plurality vias is closer to a perimeter of the first predefined area than any centers of the first plurality of vias.