Memory-centered communication apparatus in a coarse grained reconfigurable array

摘要

The present invention relates to a coarse-grained reconfigurable array, comprising: at least one processor; a processing element array including a plurality of processing elements, and a configuration cache where commands being executed by the processing elements are saved; and a plurality of memory units forming a one-to-one mapping with the processor and the processing element array. The coarse-grained reconfigurable array further comprises a central memory performing data communications between the processor and the processing element array by switching the one-to-one mapping such that when the processor transfers data from/to a main memory to/from a frame buffer, a significant bottleneck phenomenon that may occur due to the limited bandwidth and latency of a system bus can be improved.

主权项

1. A memory-centralized communication apparatus in a coarse-grained reconfigurable array (CGRA), the memory-centralized communication apparatus comprising:
at least one processor; a processing element (PE) array comprising a plurality of PEs, and a configuration cache where commands being executed by the PEs are saved; and a central memory comprising a plurality of memory units forming a one-to-one mapping with the processor and the PE array, and performing data communications between the processor and the PE array by switching the one-to-one mapping; wherein the central memory is used as a scratch pad memory of the processor and is used as a frame buffer of the PE array, wherein the PE array further comprises an address generating unit that generates a full address to the central memory using arguments received from the PEs.