发明名称 |
Mode changing circuitry |
摘要 |
A circuit includes a memory cell having a ground reference node, a switch coupled to the ground reference node, and a mode changing circuit having an output coupled to the switch. The mode changing circuit is configured to change a logic state of the output between a first output logic state and a second output logic state in response to a change in an operational voltage and/or temperature, thereby set the memory cell in a first mode in which the ground reference node is at first reference level or in a second mode in which the ground reference node is at a second reference level different from the first reference level. |
申请公布号 |
US8947949(B2) |
申请公布日期 |
2015.02.03 |
申请号 |
US201113099809 |
申请日期 |
2011.05.03 |
申请人 |
Taiwan Semiconductor Manufacturing Company, Ltd. |
发明人 |
Wang Bing;Hsu Kuoyuan (Peter) |
分类号 |
G11C7/00;G11C11/417 |
主分类号 |
G11C7/00 |
代理机构 |
Lowe Hauptman & Ham, LLP |
代理人 |
Lowe Hauptman & Ham, LLP |
主权项 |
1. A circuit comprising:
a first PMOS transistor having a first PMOS drain, a first PMOS source, and a first PMOS gate; a first NMOS transistor having a first NMOS drain, a first NMOS source, and a first NMOS gate; a second PMOS transistor having a second PMOS drain, a second PMOS source, and a second PMOS gate; and a second NMOS transistor having a second NMOS drain, a second NMOS source, and a second NMOS gate; wherein the first PMOS gate serves as an input and is configured to receive an input voltage having a voltage level determined based on an operational voltage; the first PMOS drain is coupled to the first NMOS drain and the second PMOS gate; the first PMOS source is coupled to the operational voltage; the first NMOS gate is coupled to the operational voltage; the second PMOS drain is coupled to the second NMOS drain, and serves as an output; and a driving capability of the first NMOS transistor is less than that of the first PMOS transistor. |
地址 |
TW |