Method of eDRAM DT strap formation in FinFET device structure

摘要

The specification and drawings present a new method, device and computer/software related product (e.g., a computer readable memory) are presented for realizing eDRAM strap formation in Fin FET device structures. Semiconductor on insulator (SOI) substrate comprising at least an insulator layer between a first semiconductor layer and a second semiconductor layer is provided. The (metal) strap formation is accomplished by depositing conductive layer on fins portion of the second semiconductor layer (Si) and a semiconductor material (polysilicon) in each DT capacitor extending to the second semiconductor layer. The metal strap is sealed by a nitride spacer to prevent the shorts between PWL and DT capacitors.

主权项

1. A device for an embedded dynamic random access memory (eDRAM) deep trench (DT) strap formation in a fin-shaped field effect transistor (FinFET) device structure, the device comprising:
a semiconductor on insulator (SOI) substrate comprising at least an insulator layer between a first semiconductor layer and a second semiconductor layer; a plurality of deep trench (DT) capacitors in the first semiconductor layer of the SOI substrate for the eDRAM, with a semiconductor material in each DT capacitor extending to the second semiconductor layer; a plurality of fins for FinFETs formed by selectively removing at least the second semiconductor layer up to a top of the insulator layer, where every fin of the plurality of fins comprises a portion of the second semiconductor layer and at least partially overlaps on the top of the insulator layer with at least two DT capacitors of the plurality of the DT capacitors; and a layer of a conductive material deposited in areas of the fins including side walls, the fins overlapping on the top of the insulator layer with at least two DT capacitors to form a strap between the portion of the second semiconductor layer comprised in each fin and the semiconductor material in each DT capacitor-extending to the second semiconductor layer.