| 发明名称 |
Stacked clock distribution for low power devices |
| 摘要 |
Embodiments of a clock distribution device and a method of clock distribution are described. In one embodiment, a clock distribution device includes a stacked clock driver circuit configured to perform clock signal charge recycling on input clock signals that swing between different voltage ranges and a load circuit. The stacked clock driver circuit includes stacked driver circuits configured to generate output clock signals that swing between the different voltage ranges. The load circuit includes load networks of different semiconductor types. Each of the load networks are configured to be driven by one of the output clock signals. Other embodiments are also described. |
| 申请公布号 |
US8947149(B1) |
申请公布日期 |
2015.02.03 |
| 申请号 |
US201314136137 |
申请日期 |
2013.12.20 |
| 申请人 |
NXP B.V. |
发明人 |
Kapoor Ajay;Malzahn Ralf;Meijer Rinze Ida Mechtildis Peter;Thueringer Peter |
| 分类号 |
G06F1/04;H03K3/012 |
主分类号 |
G06F1/04 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A clock distribution device, the clock distribution device comprising:
a stacked clock driver circuit configured to perform clock signal charge recycling on input clock signals that swing between different voltage ranges, wherein the stacked clock driver circuit comprises a plurality of stacked driver circuits configured to generate output clock signals that swing between the different voltage ranges; and a load circuit comprising a plurality of load networks of different semiconductor types, wherein each of the load networks is configured to be driven by one of the output clock signals. |
| 地址 |
Eindhoven NL |
