Modeling gate transconductance in a sub-circuit transistor model

摘要

A method for modeling a transistor includes providing a transistor model having at least a source node, a drain node, and a gate node, simulating operation of a device using the transistor model in a computing apparatus, and generating an offset voltage at the gate node depending on a magnitude of a current passing through the device.

主权项

1. A method for modeling a transistor, comprising:
providing a transistor model for the transistor having at least a source node, a drain node, a gate node, and a gate transconductance node coupled to the gate node; simulating operation of a device including the transistor using the transistor model in a computing apparatus; and during the simulating, generating an offset voltage at the gate transconductance node depending on a magnitude of a current passing through the transistor, wherein generating the offset voltage further comprises applying an exponential function relating gate transconductance of the transistor to the current.