发明名称 Method of manufacturing semiconductor device
摘要 Provided is a method of manufacturing a semiconductor device including a step of testing every one of through-electrodes. A second probe test is conducted to check an electrical coupling state between a plurality of copper post bumps formed on the side of the surface of a wafer and electrically coupled to a metal layer and a plurality of bumps formed on the side of the back surface of the wafer and electrically coupled to the metal layer (also another metal layer) via a plurality of through-electrodes by probing to each of the bumps on the side of the back surface while short-circuiting between the copper post bumps (electrodes). By this test, conduction between the bumps (electrodes) on the back surface side is checked.
申请公布号 US8945953(B2) 申请公布日期 2015.02.03
申请号 US201314133614 申请日期 2013.12.18
申请人 Renesas Electronics Corporation 发明人 Hasebe Akio;Makihira Naohiro;Yasumura Bunji;Kubo Mitsuyuki;Takei Fumikazu;Deguchi Yoshinori
分类号 H01L21/66 主分类号 H01L21/66
代理机构 Miles & Stockbridge P.C. 代理人 Miles & Stockbridge P.C.
主权项 1. A method of manufacturing a semiconductor device, comprising the steps of: (a) forming a first circuit layer over a first surface of a semiconductor substrate, (b) forming a plurality of through-electrodes electrically coupled to the first circuit layer in the semiconductor substrate, (c) forming a second circuit layer electrically coupled to the through-electrodes over the first circuit layer, (d) forming a plurality of first electrodes electrically coupled to the second circuit layer over the second circuit layer, (e) grinding a second surface of the semiconductor substrate opposite to the first surface to expose a portion of each of the through-electrodes and forming a plurality of second electrodes, (f) testing an electrically coupling state between the first electrodes and the second electrodes, (g) dicing the semiconductor substrate into a plurality of semiconductor chips, (h) providing a wiring substrate, and (i) mounting, among the semiconductor chips, semiconductor chips determined non-defective in the step (f) over a first main surface of the wiring substrate and electrically coupling the wiring substrate to the first electrodes, wherein the electrode pitch between the first electrodes is wider than the electrode pitch between the second electrodes, and wherein in the step (f), conduction between the second electrodes is checked while short-circuiting between the first electrodes.
地址 Kawasaki-shi JP