High speed and high jitter tolerance dispatcher

摘要

A deserializer circuit includes demultiplexer circuitry configured to receive serial data from an input and output a plurality of divided data outputs, and multiplexer circuitry configured to receive a first logic level at a first input of said multiplexer circuitry, and receive a second logic level at a second input of said multiplexer circuitry and receive one of said divided data outputs at a control input of said multiplexer circuitry. The outputs of the multiplexer circuitry produce the received serial data in a parallel form.

主权项

1. A circuit, comprising:
demultiplexer circuitry configured to receive data from an input and output a plurality of divided data signals, and multiplexer circuitry configured to receive a first logic high level at a first input of said multiplexer circuitry, and receive a second logic low level at a second input of said multiplexer circuitry and receive one of said divided data signals at a control input of said multiplexer circuitry, wherein said multiplexer circuitry is operable to select between the first logic level at the first input and the second logic level at the second input for output from the multiplexer in response to the received divided data signal, and wherein said multiplexer circuitry comprises a plurality of multiplexers, said divided data signals comprises a plurality of data streams, and a respective one of said plurality of data streams is provided to a respective control input of a respective one of said plurality of multiplexers.