发明名称 |
Core voltage reset systems and methods with wide noise margin |
摘要 |
Presented systems and methods facilitate efficient reset operation. In one embodiment, a system comprises a core domain portion an I/O domain portion and a core reset I/O by-pass component. The core domain portion is configured to operate at a nominal core domain voltage level. The I/O domain portion configured to operate at a nominal I/O domain voltage level. The core reset I/O by-pass component configured to forward a reset indication to the core domain independent of the I/O domain. In one exemplary implementation the core reset I/O by-pass component is operable to receive an input reset indication at a high domain voltage level and to convert the input reset indication to a core reset signal that is less than or substantially equal to the nominal core domain voltage, wherein the high domain is voltage higher than the core domain voltage level. |
申请公布号 |
US8947137(B2) |
申请公布日期 |
2015.02.03 |
申请号 |
US201213730668 |
申请日期 |
2012.12.28 |
申请人 |
NVIDIA Corporation |
发明人 |
Li Alan |
分类号 |
H03L7/00;H03L9/00;H01L25/03;H03K17/687;H03K19/0175;H03K19/0185 |
主分类号 |
H03L7/00 |
代理机构 |
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代理人 |
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主权项 |
1. A system comprising:
a core domain portion configured to operate at a nominal core domain voltage level; an I/O domain portion configured to operate at a nominal I/O domain voltage level that is different from said nominal core domain voltage level; and a core reset I/O by-pass component configured to forward a reset indication to the core domain portion independent of the I/O domain portion. |
地址 |
Santa Clara CA US |