I/R receiver with duty cycle synchronized power reduction

摘要

A circuit and method for reducing power consumption in an I/R receiver system includes determining a duty cycle of a command cycle comprising a series of command pulses separated by nulls and enabling and disabling selective active components of an I/R receiver system in accordance with the duty cycle. In an embodiment, the enabling of the active components commences during a null prior to the arrival of a new command pulse. In a further example embodiment, the enabling includes first enabling a first set of active components having a first settling time, waiting for at least the first settling time, and then second enabling a second set of active components having a second settling time.

主权项

1. An I/R receiver with duty cycle synchronized power reduction comprising:
an I/R receiver having a plurality of active components and being provided with an analog input receptive to a modulated carrier signal comprising a series of command cycles, where each command cycle includes a plurality of command pulses separated by nulls, where the ratio of the temporal length of the command pulses to the temporal length of said command cycle comprises a duty cycle of said command cycle, said I/R receiver being further provided with a serial digital output for a series of commands derived from said command pulses, wherein said active components of said T/R receiver include one or more of an amplifier, an automatic gain controller (AGC), a filter, a demodulator and an A/D converter; a controller having a digital input coupled to said digital output of said I/R receiver and being operative to enable and disable selected active components of said I/R receiver in accordance with said duty cycle to reduce power consumption of said I/R receiver, said controller including a command processor responsive to said series of commands and being operative to determine said duty cycle from said series of commands, and an enable/disable sequence manager coupled to said command processor, wherein said command processor provides said enable/disable sequence manager with an enable/disable start signal that is synchronized with said duty cycle; a plurality of lines coupling said enable/disable sequence manager to said I/R receiver to at least one of disable, enable, reset, and clear reset selected active components of said I/R receiver; wherein said enable/disable sequence manager is configured to enable active components of said I/R receiver in a predetermined enable sequence; wherein said enable/disable sequence manager is configured to enable at least one of said amplifier and said AGC before enabling at least one of said filter and said demodulator; and wherein said enable/disable sequence manager is configured to clear a reset of at least one of said A/D converter and said AGC after enabling at least one of said filters and said demodulator.