Transferring architected state between cores

摘要

A method and apparatus for transferring architected state bypasses system memory by directly transmitting architected state between processor cores over a dedicated interconnect. The transfer may be performed by state transfer interface circuitry with or without software interaction. The architected state for a thread may be transferred from a first processing core to a second processing core when the state transfer interface circuitry detects an error that prevents proper execution of the thread corresponding to the architected state. A program instruction may be used to initiate the transfer of the architected state for the thread to one or more other threads in order to parallelize execution of the thread or perform load balancing between multiple processor cores by distributing processing of multiple threads.

主权项

1. A system, comprising:
a plurality of processing cores including a first processing core and a plurality of target processing cores, wherein the first processing core in the plurality of processing cores is configured to gather at least a first portion and a second portion of state information associated with a first thread executing within the first processing core, where said first portion of state information is stored in registers and said second portion of state information is stored in other local memory associated with the first processing core, and to broadcast the first and second portions of the state information to the target processing cores in the plurality of processing cores; a memory that is shared between the plurality of processing cores; a state information transfer interconnect that is configured to broadcast the first and second portions of state information between the first processing core and the target processing cores included in the plurality of processing cores and bypass the memory, wherein, each of the target processing cores is configured to execute, while the first processing core executes the first thread, a second thread based on said first and second portions of the state information, each of the seconds thread being a clone of the first thread.