发明名称 Method, apparatus and system for handling data faults
摘要 Techniques and mechanisms for handling data faults in a memory system which includes multiple integrated circuit (IC) dies, each die including a respective one of multiple memory arrays. In an embodiment, control logic monitors for a die failure of the multiple dies, and further monitors for a request to perform error correction for the multiple memory arrays. Each of the multiple memory arrays may store a respective vertical error correction code specific to data of that memory array. Another IC die may store a Bose, Ray-Chaudhuri, Hocquenghem (BCH) code of a horizontal codeword which spans the multiple memory arrays. In another embodiment, the BCH code is available to decode logic for data recovery operations in response to a die failure, where the BCH code is further available to the decode logic for error correction operations when all of the memory arrays are operative.
申请公布号 US8949698(B2) 申请公布日期 2015.02.03
申请号 US201213629295 申请日期 2012.09.27
申请人 Intel Corporation 发明人 Kwok Zion S.;Nelson Scott
分类号 H03M13/00;G11C29/00 主分类号 H03M13/00
代理机构 Blakely, Sokoloff, Taylor & Zafman LLP 代理人 Blakely, Sokoloff, Taylor & Zafman LLP
主权项 1. A device comprising: control logic to monitor for a die failure of multiple dies each including a respective one of multiple memory arrays, the control logic further to monitor for a request to perform error correction for the multiple memory arrays; and decoder logic coupled to the control logic, wherein, if the request is detected while each of the multiple dies is operative, the decoder logic to perform the error correction, including:the decoder logic to perform a first horizontal Bose, Ray-Chaudhuri, Hocquenghem (BCH) decode operation based on a first BCH code of a first die coupled to the multiple dies, the first BCH code generated based on respective data of each of the multiple memory arrays; and the decoder logic to perform first vertical error correction (VEC) decode operations based on a result of the BCH decode operation and VEC codes each of a respective memory array of the multiple memory arrays, wherein, for each of the VEC codes, the VEC code is specific to data of the respective memory array which includes the VEC code; wherein, if the die failure is indicated, the decoder logic to perform a second horizontal BCH decode operation based on the first BCH code for recovery of data of a failed die.
地址 Santa Clara CA US