System and method to overcome wander accumulation to achieve precision clock distribution over large networks

摘要

A system and method for synchronizing clocks across a packet-switched network eliminates wander accumulation to enable precision clock distribution across a large network. In addition to standard Precision Time Protocol (PTP) synchronization messages or similar time synchronization messages, each clock regenerator stage receives a grand clock error message from the previous stage, updates this error message with its own stage clock error, and then transmits the updated grand clock error to the next stage. This enables the synchronization algorithm to compensate for the error of the previous stage, effectively locking each clock regenerator stage to the grand master clock directly.

主权项

1. A clock synchronization system for use in a network comprising a grand master clock, a first clock regenerator, and a second clock regenerator, wherein:
the grand master clock includes a primary precision timing source; the first clock regenerator is operatively connected to the grand master clock, and to the second clock regenerator, wherein the first clock regenerator includes:
a first local clock; anda first synchronization processing unit for synchronizing the first local clock to the grand master clock and configured to:
receive a first master-to-slave message from the grand master clock;send a first slave-to-master message to the grand master clock;calculate a first master-to-slave path delay and a first slave-to-master path delay based at least in part on the first master-to-slave message and the first slave-to-master message;calculate a first stage clock error equal to one half of a difference between the first slave-to-master path delay and the first master-to-slave path delay;generate a first grand clock error equal to a sum of the first stage clock error and a grand clock baseline error, wherein the grand clock baseline error is set equal to zero; andsynchronize the first local clock to the grand master clock based at least in part on the first stage clock error and the grand clock baseline error;transmit the first grand clock error to the second clock regenerator; and the second clock regenerator is operatively connected to the first clock regenerator, wherein the second clock regenerator includes:
a second local clock; anda second synchronization processing unit for synchronizing the second local clock to the grand master clock and configured to:
receive a second synchronization message from the first clock regenerator;receive a second delay response message from the first clock regenerator;receive and store the first grand clock error from the first clock regenerator;calculate a second master-to-slave path delay based at least in part on the second synchronization message;calculate a second slave-to-master path delay based at least in part on the second delay response message;calculate a second stage clock error equal to one half of a difference between the second slave-to-master path delay and the second master-to-slave path delay;calculate a second grand clock error equal to a sum of the first grand clock error and the second stage clock error; andsynchronize the second local clock to the grand master clock based at least in part on the second stage clock error and the first grand clock error.