Delay circuit and latency control circuit of memory, and signal delay method thereof

摘要

A delay circuit includes a delay unit configured to generate a delayed transfer signal by delaying a transfer signal corresponding to a first signal or a second signal, a distinguishment signal generation unit configured to generate a distinguishment signal which represents to what signal the transfer signal correspond between the first signal and the second signal and a delayed signal generation unit configured to output the delayed transfer signal as a first delayed signal or a second delayed signal in response to the distinguishment signal.

主权项

1. A delay circuit, comprising:
a delay unit configured to generate a delayed transfer signal by delaying a transfer signal wherein the transfer signal is enabled when a first signal or a second signal is applied; a distinguishment signal generation unit configured to generate a distinguishment signal which has a first value when the transfer signal is enabled in response to the applied first signal, and has a second value when the transfer signal is enabled in response to the applied second signal; and a delayed signal generation unit configured to output the delayed transfer signal as a first delayed signal when the distinguishment signal has the first value, or output the delayed transfer signal as a second delayed signal when the distinguishment signal has the second value.