| 摘要 |
A chip package includes a stack of semiconductor dies or chips that are offset from each other, thereby defining a terrace with exposed pads. Moreover, surfaces of each of the semiconductor dies in the stepped terrace include two rows of first pads approximately parallel to edges of the semiconductor dies. Furthermore, the chip package includes a high-bandwidth ramp component, which is positioned approximately parallel to the terrace, and which has a surface that includes second pads arranged in at least two rows of second pads for each of the semiconductor dies. The second pads are electrically and mechanically coupled to the exposed first pads by connectors. Consequently, the electrical contacts in the chip package may have a conductive, a capacitive or, in general, a complex impedance. Furthermore, the chips and/or the ramp component may be positioned relative to each other using a ball-and-pit alignment technique. |
