| 摘要 |
PURPOSE:To simplify circuits by constructing element alpha<i> of GAROWA form GF (2<m>) with binary counter. CONSTITUTION:The portion that generates element alpha<1> is replaced with binary counter 6, the data which has been changed in the array order of vecotor from a1, a2...to a3, a1, a6, a2, a5, a4 is input into input terminal 10, the counted value of counter 6 is changed as sequential system -(7) by the system clock related to data input and the lead-solomon code obtained by the multiplication of multiplier 2 is output from the output terminal 20. The circuit includes shift register 1 with parallel m bits, exclusive ''OR'' gate 4 and selecter 5 of information unit and inspection unit. |
