| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a latency counter capable of increasing signal quality of an output internal command.SOLUTION: A latency counter comprises a point shift type FIFO circuit 300 to be controlled with a count value of a counter circuit 200. The point shift type FIFO circuit 300 comprises: a wired OR circuit 351 for synthesizing output of latch circuits 330-0 to 330-3; a wired OR circuit 352 for synthesizing output of latch circuits 330-4 to 330-7; a gate circuit 353 for synthesizing output of the wired OR circuits 351 and 352; and reset circuits 354 and 355 for respectively resetting the wired OR circuits 351 and 352 on the basis of the count value of the counter circuit 200. High signal quality can be obtained since an output load is decreased as compared with such a case that the output of all latch circuits are made to be wired-OR connected.</p> |
