发明名称 複数の平行な導電材料含有構造を備える半導体構造およびスタティック・ランダム・アクセス・メモリ(SRAM)・セル、ならびに半導体構造を形成する方法
摘要 <p>A common cut mask is employed to define a gate pattern and a local interconnect pattern so that local interconnect structures and gate structures are formed with zero overlay variation relative to one another. A local interconnect structure may be laterally spaced from a gate structure in a first horizontal direction, and contact another gate structure in a second horizontal direction that is different from the first horizontal direction. Further, a gate structure may be formed to be collinear with a local interconnect structure that adjoins the gate structure. The local interconnect structures and the gate structures are formed by a common damascene processing step so that the top surfaces of the gate structures and the local interconnect structures are coplanar with each other.</p>
申请公布号 JP5660651(B2) 申请公布日期 2015.01.28
申请号 JP20140509285 申请日期 2012.01.16
申请人 发明人
分类号 H01L21/8244;H01L27/11 主分类号 H01L21/8244
代理机构 代理人
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