发明名称 インバータ回路および表示装置
摘要 <P>PROBLEM TO BE SOLVED: To provide an inverter circuit that is made low in power consumption and fast compatibly without increasing a breakdown voltage, and a display device including the inverter circuit. <P>SOLUTION: In the inverter circuit comprising seven Tr's and three C's, capacitive elements C<SB POS="POST">1</SB>, C<SB POS="POST">3</SB>are connected between a gate and a source of transistors Tr<SB POS="POST">5</SB>, Tr<SB POS="POST">2</SB>on a side of a high voltage line L<SB POS="POST">H</SB>, and capacitive elements C<SB POS="POST">1</SB>, C<SB POS="POST">2</SB>are connected between the gate of the transistor Tr<SB POS="POST">5</SB>and an input terminal IN in series. Consequently, when a voltage value of the side of the high voltage line L<SB POS="POST">H</SB>is output, the transistors Tr<SB POS="POST">7</SB>, Tr<SB POS="POST">5</SB>and Tr<SB POS="POST">2</SB>raise gate voltages and source voltages from off states to turn on one after another while varying gate-source voltages, and when the transistor Tr<SB POS="POST">5</SB>turns off finally, the transistor Tr<SB POS="POST">7</SB>outputs the voltage value of the side of the high voltage line L<SB POS="POST">H</SB>as an output voltage. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP5659906(B2) 申请公布日期 2015.01.28
申请号 JP20110073022 申请日期 2011.03.29
申请人 发明人
分类号 H03K19/0944;H03K19/0175 主分类号 H03K19/0944
代理机构 代理人
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