| 摘要 |
<p>PROBLEM TO BE SOLVED: To inhibit an increase in Cgd (gate-drain parasitic capacitance) while reducing gate resistance thereby to improve a high frequency gain of a semiconductor device.SOLUTION: In a semiconductor device, source wiring 100 including a pad electrode, drain wiring 104 including a pad electrode, a contact 106, a source electrode 108, a drain electrode 110, a first gate electrode 112 and a second gate electrode 114 are formed on a substrate 127 where an FET layer structure is formed. One ends of the first gate electrode 112 and the second gate electrode 114 are connected by gate wiring 116 which is a signal input part and the other ends are connected by second gate wiring 118 which is a termination part. The source wiring 100 and the drain wiring 104, and the first gate electrode 112 and the second gate electrode 114 are arranged to be parallel with each other in a longer direction.</p> |
