发明名称 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
摘要 A manufacturing method of a semiconductor device in which the threshold is corrected is provided. In a semiconductor device including a plurality of transistors each includes a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and a charge trap layer between the gate electrode and the semiconductor, electrons are trapped in the charge trap layer by performing heat treatment and, simultaneously, keeping a potential of the gate electrode higher than that of the source or drain electrode for 1 second or more. By this process, the threshold increases and Icut decreases. A circuit for supplying a signal to the gate electrode and a circuit for supplying a signal to the source or drain electrode are electrically separated from each other. The process is performed in the state where the potential of the former circuit is set higher than the potential of the latter circuit.
申请公布号 US2015024577(A1) 申请公布日期 2015.01.22
申请号 US201414330481 申请日期 2014.07.14
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 KATO Kiyoshi;TAKEMURA Yasuhiko;TANAKA Tetsuhiro;INOUE Takayuki;TAKEUCHI Toshihiko;YAMANE Yasumasa;YAMAZAKI Shunpei
分类号 G11C16/04;H01L27/115;G11C16/20 主分类号 G11C16/04
代理机构 代理人
主权项 1. A manufacturing method of a semiconductor device comprising: a plurality of transistors arranged in a matrix, the transistors each comprising a first semiconductor, an electrode electrically connected to the first semiconductor, a gate electrode, and a charge trap layer between the gate electrode and the first semiconductor, a first circuit configured to supply a first signal to the gate electrodes of the plurality of transistors, a second circuit configured to supply a second signal to the electrodes of the plurality of transistors, a first wiring and a second wiring electrically connected to the first circuit, and a third wiring and a fourth wiring electrically connected to the second circuit, the manufacturing method comprising the steps of: setting a first potential of the first wiring at a potential higher than a second potential of the third wiring by 1 V or more,performing heat treatment on the plurality of transistors at a temperature higher than or equal to 125° C. and lower than or equal to 450° C., andapplying a third potential of the gate electrode higher than a fourth potential of the electrode for 1 second or more during the heat treatment.
地址 Atsugi-shi JP