Intrinsic Channel Planar Field Effect Transistors Having Multiple Threshold Voltages

摘要

Intrinsic channels one or more intrinsic semiconductor materials are provided in a semiconductor substrate. A high dielectric constant (high-k) gate dielectric layer is formed on the intrinsic channels. A patterned diffusion barrier metallic nitride layer is formed. A threshold voltage adjustment oxide layer is formed on the physically exposed portions of the high-k gate dielectric layer and the diffusion barrier metallic nitride layer. An anneal is performed to drive in the material of the threshold voltage adjustment oxide layer to the interface between the intrinsic channel(s) and the high-k gate dielectric layer, resulting in formation of threshold voltage adjustment oxide portions. At least one work function material layer is formed, and is patterned with the high-k gate dielectric layer and the threshold voltage adjustment oxide portions to form multiple types of gate stacks.

主权项

1. A semiconductor structure comprising:
a first field effect transistor including a first gate stack containing a first high dielectric constant (high-k) dielectric portion and a first gate electrode contacting said first high-k dielectric portion, said first high-k dielectric portion comprises a first high-k dielectric material and overlies a first semiconductor channel region; a second field effect transistor including a second gate stack containing a threshold voltage adjustment oxide portion, a second high-k dielectric portion comprising said first high-k dielectric material, and a second gate electrode contacting said second high-k dielectric portion, wherein said threshold voltage adjustment oxide portion comprises a second high-k dielectric material different from said first high-k dielectric material and overlies a second semiconductor channel region; and a third field effect transistor including a third gate stack containing at least a third high-k dielectric portion comprising said first high-k dielectric material and a third gate electrode contacting said third high-k dielectric portion, wherein said first and third field effect transistors are of complementary types.