Architecture to Improve Cell Size for Compact Array of Split Gate Flash Cell with Buried Common Source Structure

摘要

Some embodiments of the present disclosure relates to an architecture to create split gate flash memory cell that has lower common source (CS) resistance and a reduced cell size by utilizing a buried conductive common source structure. A two-step etch process is carried out to create a recessed path between two split gate flash memory cells. A single ion implantation to form the common source also forms a conductive path beneath the STI region that connects two split gate flash memory cells and provide potential coupling during programming and erasing and thus electrically connect the common sources of memory cells along a direction that forms a CS line. The architecture contains no OD along the source line between the cells, thus eliminating the effects of CS rounding and CS resistance, resulting in a reduced space between cells in an array. Hence, this particular architecture reduces the resistance and the buried conductive path between several cells in an array suppresses the area over head.

主权项

1. A memory device comprising:
a first pair of split gate flash memory cells residing within a first active region, the first active region having an upper surface in a semiconductor body, wherein the first pair of split gate flash memory cells share a first shared erase gate having a dish shaped surface that extends below the upper surface of the first active region; and a first shared common source region disposed below the dish shaped surface of the first erase gate in the first active region.