System Clock Jitter Correction

摘要

A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.

主权项

1. A method for analog-to-digital converter (ADC) data jitter correction, the method comprising:
accepting an analog data signal; sampling an amplitude of the analog data signal using a first system clock signal having a first frequency, to create a first reference digitized signal; sampling the amplitude of the analog data signal using a second system clock signal, to create a second reference digitized signal; adjusting a phase of the second reference digitized signal to create a phase-adjusted second reference digitized signal; subtracting the first reference digitized signal from the phase-adjusted second reference digitized signal, to create an error signal; and, in response to finding the error signal, deriving a jitter estimate.