METHOD FOR FABRICATING A FINFET IN A LARGE SCALE INTEGRATED CIRCUIT

摘要

Systems and methods of fabricating a FinFET in large scale integrated circuit are disclosed. One illustrative method relates to a dummy gate process, wherein the fin structure is only formed in the gate electrode region by performing a photolithography process and an etching of a first dummy gate on a flat STI surface using chemical mechanical polishing, forming drain and source regions, depositing a medium dielectric layer, polishing the medium dielectric layer till the top of the first dummy gate is exposed through the chemical mechanical polishing process again, removing the dummy gate material via a dry etching and a wet etching, and continuously etching the STI dielectric layer with the hard mask formed by the medium dielectric layer, thereafter performing the deposition of real gate dielectric and gate electrode material to complete the device structure.

主权项

1. A method for fabricating a FinFET, comprising the following steps:
1) forming a STI isolation layer on a bulk silicon substrate, performing a well implantation and channel ion implantation to an active region and performing an annealing; 2) exposing a silicon surface of the active region, depositing a sacrificial gate oxide layer, forming a dummy gate on the sacrificial gate oxide layer, wherein the top of the dummy gate is covered by a composite hard mask of silicon oxide and silicon nitride; 3) removing the sacrificial gate oxide layer covered on the drain and source regions, depositing a thin film of silicon nitride as an implantation mask for the drain and source regions to perform a drain and source LDD implantation and a Halo implantation, and performing a rapid flash annealing of milliseconds; 4) depositing a silicon nitride layer, performing a photolithgraphy process, performing an anisotropic dry etching to the silicon nitride layer with the photoresist as a mask, to form silicon nitride sidewalls of the dummy gate and expose the silicon mesa of the drain and source regions, and then performing an etch-back process to the STI isolation layer around the silicon mesa of the drain and source regions; 5) removing the photoresist, performing a drain and source epitaxial growth with the exposed silicon mesa as a crystal seed window, and then performing an additional drain and source implantation and a flash annealing of millisecond to form the drain and source regions; 6) depositing a silicon oxide layer so as to cover the entire surface of silicon wafer; then performing a thinning and planarization of the silicon oxide layer through a chemical mechanical polishing process with the silicon nitride layer on the top of the dummy gate as a stop layer; then performing a dry etch-back to the silicon oxide layer till ⅓-½ of the height of the dummy gate; 7) depositing a silicon nitride layer, performing a thinning process to the silicon nitride layer by a chemical mechanical polishing process till the silicon oxide layer on top of the dummy gate or the dummy gate is exposed; with a remaining silicon nitride layer as a hard mask, removing the dummy gate to expose the STI isolation layer under the dummy gate; performing a dry etch-back process to the STI isolation layer to form the fin-shaped channel region; and 8) etching the silicon oxide layer remaining on the top and sidewalls of the fin-shaped channel region, depositing a real gate dielectric and gate electrode material to complete the device structure.