发明名称 DEPENDENT INSTRUCTION SUPPRESSION
摘要 A method includes suppressing execution of at least one dependent instruction of a first instruction by a processor responsive to an invalid status of an ancestor load instruction associated with the first instruction. A processor includes an instruction pipeline having an execution unit to execute instructions, a load store unit for retrieving data from a memory hierarchy, and a scheduler unit. The scheduler unit selects for execution in the execution unit a first load instruction having at least one dependent instruction linked to the first load instruction for data forwarding from the load store unit and suppresses execution of a second dependent instruction of the first dependent instruction responsive to an invalid status of the first load instruction.
申请公布号 US2015026685(A1) 申请公布日期 2015.01.22
申请号 US201313943264 申请日期 2013.07.16
申请人 Advanced Micro Devices, Inc. 发明人 Spadini Francesco;Achenbach Michael;Talpes Emil;Venkataramanan Ganesh
分类号 G06F9/48;G06F9/38 主分类号 G06F9/48
代理机构 代理人
主权项 1. A method comprising: suppressing execution of at least one dependent instruction of a first instruction by a processor responsive to an invalid status of an ancestor load instruction associated with the first instruction.
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