| 摘要 |
A power semiconductor device includes an output transistor, a control circuit connected with a gate of the output transistor, a first discharge route from a first node to a ground terminal, and a second discharge route from the first node to the ground terminal. In a usual turn-off, only the first discharge route is used. When a load abnormality occurs, both of the first and second discharge routes are used. The second discharge route contains a discharge transistor and a countercurrent prevention device. The discharge transistor is connected between the first node and the second node. The countercurrent prevention device prevents a flow of current from the third node to the second node. At least, in an OFF period, the control circuit sets the gate voltage of the discharge transistor to a high level. |
| 主权项 |
1. A power semiconductor device, comprising:
an output transistor connected between a power supply terminal and an output terminal; a first discharge transistor having a drain connected with a first node connected to a gate of the output transistor and a source connected to the output terminal; a second discharge transistor having a drain connected with the first node, wherein a source and a back gate of the second discharge transistor are connected with a second node; a countercurrent prevention device connected between the second node and a third node to prevent a current flow from the third node to the second node, a control circuit configured to control charging and discharging of the first node, an ON/OFF condition of the first discharge transistor, an ON/OFF condition of the second discharge transistor, and a connection between the third node and a ground terminal, in response to an input signal inputted to an input terminal, wherein, when the input signal is activated, the control circuit turns on a transistor connected between the third node and the ground terminal and controls, in response to occurrence of load abnormality, the charging of the first node, the ON/OFF condition of the first discharge transistor and the ON/OFF condition of the second discharge transistor, and wherein, when the input signal is deactivated, the control circuit stops the charging of the first node, turns on the first and second discharge transistors, and turns off the transistor connected between the third node and the ground terminal. |
