COMPENSATION SCHEME FOR NON-VOLATILE MEMORY

摘要

Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell.

主权项

1. A monolithic three-dimensional integrated circuit, comprising:
a three-dimensional memory array including a plurality of memory cells, the plurality of memory cells includes a first memory cell and a second memory cell, the first memory cell is formed above the second memory cell, the second memory cell is formed above a substrate, the first memory cell and the second memory cell are arranged in a vertical column that is perpendicular to the substrate; a plurality of voltage generators, the plurality of voltage generators generates a plurality of bit line voltage options associated with a programming operation; and a first memory cell programming circuit in communication with the first memory cell, the first memory cell programming circuit determines a first state associated with the first memory cell and determines an upper current threshold based on the first state, the first memory cell programming circuit selects a first bit line voltage of the plurality of bit line voltage options based on whether an output current associated with the first memory cell is greater than the upper current threshold, the first memory cell programming circuit causes the first bit line voltage to be applied to the first memory cell during the programming operation.