发明名称 FIN Field Effect Transistors Having Multiple Threshold Voltages
摘要 A high dielectric constant (high-k) gate dielectric layer is formed on semiconductor fins including one or more semiconductor materials. A patterned diffusion barrier metallic nitride layer is formed to overlie at least one channel, while not overlying at least another channel. A threshold voltage adjustment oxide layer is formed on the physically exposed portions of the high-k gate dielectric layer and the diffusion barrier metallic nitride layer. An anneal is performed to drive in the material of the threshold voltage adjustment oxide layer to the interface between the intrinsic channel(s) and the high-k gate dielectric layer, resulting in formation of threshold voltage adjustment oxide portions. At least one workfunction material layer is formed, and is patterned with the high-k gate dielectric layer and the threshold voltage adjustment oxide portions to form multiple types of gate stacks straddling the semiconductor fins.
申请公布号 US2015021699(A1) 申请公布日期 2015.01.22
申请号 US201313945095 申请日期 2013.07.18
申请人 International Business Machines Corporation 发明人 Ando Takashi;Chudzik Michael P.;Kannan Balaji;Krishnan Siddarth A.;Kwon Unoh;Narayanan Vijay
分类号 H01L27/088;H01L21/28 主分类号 H01L27/088
代理机构 代理人
主权项 1. A semiconductor structure comprising: a first fin field effect transistor including a first gate stack that contains a first high dielectric constant (high-k) dielectric portion comprising a first high-k dielectric material straddling a first semiconductor fin, and a first gate electrode contacting said first high-k dielectric portion; a second fin field effect transistor including a second gate stack that contains a threshold voltage adjustment oxide portion comprising another dielectric material different from said first high-k dielectric material and straddling a second semiconductor fin, a second high-k dielectric portion comprising said first high-k dielectric material, and a second gate electrode contacting said second high-k dielectric portion; and a third fin field effect transistor including a third gate stack that contains a third high-k dielectric portion comprising said first high-k dielectric material and straddling a third semiconductor fin, and a third gate electrode contacting said third high-k dielectric portion, wherein said first and second fin field effect transistors are transistors of a first conductivity type, said third fin field effect transistor is a transistor of a second conductivity type that is the opposite of said first conductivity type.
地址 Armonk NY US