发明名称 CACHE SYSTEM FOR MANAGING VARIOUS CACHE LINE CONDITIONS
摘要 A cache controller configured to detect a wait type (i.e., a wait event) associated with an imprecise collision and/or contention event is disclosed. The cache controller is configured to operatively connect to a cache memory device, which is configured to store a plurality of cache lines. The cache controller is configured to detect a wait type due to an imprecise collision and/or collision event associated with a cache line. The cache controller is configured to cause transmission of a broadcast to one or more transaction sources (e.g., broadcast to the transaction sources internal to the cache controller) requesting the cache line indicating the transaction source can employ the cache line.
申请公布号 US2015026411(A1) 申请公布日期 2015.01.22
申请号 US201313952710 申请日期 2013.07.29
申请人 LSI Corporation 发明人 Lippert Gary M.;Gehman Judy M.;Greenfield Scott E.;Meyer Jerome M.;Nystuen John M.
分类号 G06F12/08 主分类号 G06F12/08
代理机构 代理人
主权项 1. An apparatus comprising: a cache controller configured to operatively couple to a cache memory device, the cache memory device configured to store a plurality of cache lines, the cache controller configured to detect a wait type due to an at least one of an imprecise collision event or an imprecise contention event associated with at least one cache line of the plurality of cache lines; and cause transmission of a broadcast to at least one transaction source requesting the at least one cache line, the broadcast indicating the at least one transaction source can employ the at least one cache line.
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