| 摘要 |
<p>#CMT# #/CMT# The circuit has a fork (F) with two branches (B0, B1), where each branch is connected to logic gates, so that the logic gates receive a branch end signal from terminals (X0, X1) in input. Derivation circuits (2a, 2b) derive the branch end signal at each logic gate to form derived signals (X0', X1'). A blocking circuit includes muller doors (G0, G1) and receives the derived signal in input. The blocking circuit is configured to prevent propagation of data output signals (S0, S1) and acknowledgment signal (Eack) when the branch end signals are in different logical states. #CMT# : #/CMT# An independent claim is also included for a method for reducing sensitivity to delays of an asynchronous circuit. #CMT#USE : #/CMT# Asynchronous circuit e.g. demultiplexing circuit, merge circuit and buffer circuit. #CMT#ADVANTAGE : #/CMT# The design of the circuit increases robustness of the circuit to variations of propagation delays in isochronous fork. #CMT#DESCRIPTION OF DRAWINGS : #/CMT# The drawing shows a schematic view illustrating a demultiplexing function after a design technique of an asynchronous circuit. B0, B1 : Branches Eack : Acknowledgment signal F : Fork G0, G1 : Muller doors S0, S1 : Data output signals X0, X1 : Terminals X0', X1' : Derived signals 2a, 2b : Derivation circuits.</p> |
