Memory device redundancy management system

摘要

A system for managing redundancy in a memory device includes memory arrays and associated periphery logic circuits, and redundant memory arrays and associated redundant periphery logic circuits. The memory arrays and a first set of logic circuits associated with the periphery logic circuits corresponding to the memory arrays are connected to the power supply by way of memory I/O switches. The redundant memory arrays and associated redundant periphery logic circuits are connected to the power supply by way of redundant I/O switches. The memory and redundant I/O switches are switched on/off based on an acknowledgement signal generated during a built-in-self-test (BIST) operation of the memory device.

主权项

1. A system for managing redundancy in a memory device, wherein the memory device includes a first memory array and a first periphery logic circuit associated therewith, and at least one redundant memory array and a redundant periphery logic circuit associated therewith, wherein the first periphery logic circuit includes first and second logic circuits, and wherein the second logic circuit includes first and second sets of logic circuits, the system comprising:
a memory input/output (I/O) switch, connected to a power supply, the first memory array, and the first periphery logic circuit, wherein the memory I/O switch is configured to be switched on during a memory built-in-self-test (BIST) operation for detecting at least one defect in the first memory array and switched off for disabling a supply of power to the first memory array, the first logic circuit, and the first set of logic circuits, based on the detection of the at least one defect; and a redundant I/O switch, connected to the power supply, the redundant memory array, and the redundant periphery logic circuit, wherein the redundant I/O switch is configured to be switched on when the redundant memory array and the redundant periphery logic circuit are substituted for the first memory array and the first periphery logic circuit, respectively, based on the detection of the at least one defect, and switched off when the redundant memory array and the redundant periphery logic circuit are not in use, wherein the second set of logic circuits is connected to the power supply to receive a continuous supply of power therefrom to enable shifting of data stored in the first memory array to the redundant memory array, based on the detection of the at least one defect, wherein the second logic circuit includes at least one of a read latch, an output driver, a write latch, and a redundancy decoder, and wherein the read latch includes:
a first latch circuit connected to the power supply by way of the memory I/O switch and having a data input terminal connected to the first logic circuit, wherein the memory I/O switch disables a supply of power to the first latch circuit based on the detection of the at least one defect;a first multiplexer having a first input terminal connected to an output terminal of the first latch circuit, a second input terminal connected to an output terminal of a second latch circuit corresponding to a second periphery logic circuit associated with a second memory array, and a select terminal for receiving a shift enable signal, wherein the first multiplexer selectively outputs at least one of the outputs of the first and second latch circuits at an output terminal thereof; anda first buffer circuit having an input terminal connected to the output terminal of the first multiplexer and an output terminal that generates a read output of the first memory array, wherein the first multiplexer and the first buffer circuit are connected to the power supply for receiving the continuous supply of power.