Systems and methods for partial retention synthesis

摘要

A retention synthesis application provides a means of analyzing a circuit design, functional test sequences, and the associated power specification to identify registers that do not need retention when a block is powered down. Reducing the number of retention registers reduces power consumption and chip area. The retention synthesis application is based, at least in part, upon symbolic simulation. In symbolic simulation, a symbol is used to represent a value that can be either 0 or 1 and the propagation of symbols is traced through the simulation.

主权项

1. A method for identifying retention status of registers of a circuit, the method comprising the steps of:
performing symbolic simulation for one or more simulation cycles starting at the beginning of the one or more simulation cycles; replacing each register value with a multiplexer, a select of the multiplexer equal to 0 connecting to the register value and another input of the multiplexer connects to a symbol; collecting a first symbolic trace at an output and building a first miter with a logic value of the first symbolic trace; collecting a second symbolic trace in design registers and building a second miter with a logic value of each register value; producing a Boolean function by implementing an OR logic gate, using a processor, that ORs the output of the first miter and the output of the second miter, if the output is 0 the circuit behavior has not changed, thereby identifying a non-retention register, and if the output is 1, the circuit behavior has changed, thereby identifying a retention register; and determining a set of non-retention registers that allow the output to remain 0.