发明名称 Methods and systems for signal processing of neural data
摘要 In an embodiment, an electrical-line-noise canceller includes a phase detector, a phase lock loop, a zero-crossing detector, and an adaptive filter. The phase detector is configured to receive a composite input signal including an input neural signal combined with electrical line noise and to detect a phase of the electrical line noise. The phase lock loop is coupled to the phase detector and is configured to lock to the phase of the electrical line noise. The zero-crossing detector is coupled to the phase lock loop and is configured to detect zero crossings of an output of the phase lock loop. The adaptive filter is coupled to the zero-crossing detector and is configured to remove the electrical line noise from the composite input signal and output a filtered neural signal that is substantially similar to the input neural signal.
申请公布号 US8938291(B1) 申请公布日期 2015.01.20
申请号 US201012906673 申请日期 2010.10.18
申请人 Blackrock Microsystems, LLC 发明人 Azarnasab Ehsan;Nilsen Erik Alfonso
分类号 A61B5/0476;H03K5/00;G06F9/455;A61B5/00;A61B5/04;A61B5/048 主分类号 A61B5/0476
代理机构 Dorsey & Whitney LLP 代理人 Dorsey & Whitney LLP
主权项 1. A neuralphysiological data acquisition system comprising: an electrode array configured to receive and transmit analog neural signals; a digitizer/amplifier module coupled to the electrode array and configured to amplify and convert the analog neural signals to digital neural signals; and a neural signal processor comprising an electrical-line-noise canceller coupled to the digitizer/amplifier module and configured to receive a composite input signal comprising the digital neural signals and electrical line noise, wherein the electrical-line-noise canceller is further configured to selectively filter the electrical line noise from the composite input signal and output filtered neural signals, wherein the electrical-line-noise canceller includes: a phase detector configured to receive and detect a phase of the composite input signal, the phase detector including: a sinusoid generator configured to generate a sinusoid for multiplication by the composite input signal to generate a demodulated noise signala low pass filter configured to receive the demodulated noise signal;a proportional-integral-derivative controller coupled to the low pass filter; anda phase interpolator coupled to the proportional-integral-derivative controller;a phase lock loop coupled to the phase detector and configured to lock to the phase of the electrical line noise;a zero-crossing detector coupled to the phase lock loop and configured to detect zero crossings of an output of the phase lock loop; andan adaptive filter coupled to the zero-crossing detector and configured to remove the electrical line noise from the composite input signal and output the filtered neural signals that are substantially similar to the digital neural signals; and wherein: the composite input signal is modeled as: x(t)=N(t)+A(t)sin(2π(fLN+δf(t))t+δφ(t)),where N(t) is the input neural signal, A(t) is an amplitude signal of the electrical line noise, t is a variable representing time, fLN is nominal line noise frequency of the electrical line noise, δf(t) is frequency deviation of the electrical line noise from nominal frequency fLN, and δφ(t) is phase deviation of the electrical line noise;the sinusoid is modeled as: y(t)=cos(φ(t)−π/2),where φ(t) is estimated phase of the electrical line noise; andφ(t) is modeled as: φ(t)=2πfLN*t+Δφ(t),where Δφ(t) is estimated phase difference Δφe(t) output by the proportional-integral-derivative controller once every D samples, or interpolated phase difference Δφi(t) output by the phase interpolator for every sample in between the D-sampled estimated phase difference Δφe(t), or phase deviation δφ(t) output by the phase lock loop; andthe low pass filter is configured to output an error signal that is valid once every D samples and that is modeled as: error(t)=B(t)sin(Δφe(t)),where B(t) is an approximation of A(t);the proportional-integral-derivative controller is configured to output estimated phase difference Δφe(t) once every D samples that is also output by the phase interpolator once every D samples to the phase lock loop, where estimated phase difference Δφe(t) is modeled as: Δφe(t)=Kp*error(t=n*D)+Ki*(Δφe(t=n*D−D)+error(t=n*D)*1/fs)+Kd*(error(t=n*D)−error(t=n*D−D)),where Kp, Ki, and Kd are, respectively, a proportional weighting factor, an integral weighting factor, and a derivative weighting factor of the proportional-integral-derivative controller, n is 0, 1, 2, 3, . . . , error(t=n*D) represents the output of the low pass filter at a particular valid time sample t=n*D, Δφe(t=n*D−D) represents estimated phase difference Δφe(t) at an immediately preceding valid time sample t=n*D−D, fs is a sampling frequency of the phase detector, and error(t=n*D−D) represents the output of the low pass filter at the immediately preceding valid time sample t=n*D−D.
地址 Salt Lake City UT US