Confirm instruction for processing vectors

摘要

The described embodiments include a processor with a fault status register (FSR) that executes a Confirm instruction. In these embodiments, when executing the Confirm instruction, the processor receives a predicate vector that includes N elements. For a first set of bit positions in the FSR for which corresponding elements of the predicate vector are active, the processor determines if at least one of the first set of bit positions in the FSR holds a predetermined value. When at least one of the first set of bit positions in the FSR holds the predetermined value, the processor causes a fault in the processor.

主权项

1. A method for executing program code in a vector processor that includes a fault status register (FSR) with N bit positions, comprising:
receiving a predicate vector, wherein the predicate vector has N elements; for a first set of bit positions in the FSR for which corresponding elements of the predicate vector are active,
determining if at least one of the first set of bit positions in the FSR holds a predetermined value; andwhen at least one of the first set of bit positions in the FSR holds the predetermined value, causing a fault in the processor; and not causing a fault in the processor when none of the first set of bit positions in the FSR holds the predetermined value or when one or more of a second set of bit positions in the FSR for which corresponding elements of the predicate vector are inactive hold the predetermined value.