发明名称 PLL(Phase-Locked Loop) direct modulator and frequency gain mismatch compensation method in the modulator
摘要 <p>The present invention relates to a PLL direct modulator and a frequency gain mismatch compensation method in the modulator. A PLL direct modulator in accordance with the present invention includes: a phase-frequency detector (PFD), a charge pump (CP), a loop filter, a voltage-controlled oscillator (VCO), a divider, and a sigma-delta modulator, wherein a frequency gain mismatch compensator is installed between the divider and the VCO to modulate a frequency of the VCO by receiving a frequency signal from the divider and modulation data supplied from the outside. According to the present invention, it is possible to reduce a frequency gain mismatch in the PLL modulator by compensating the frequency gain mismatch through the frequency gain mismatch compensator.</p>
申请公布号 KR101483855(B1) 申请公布日期 2015.01.16
申请号 KR20130044225 申请日期 2013.04.22
申请人 发明人
分类号 H03L7/085;H03L7/183 主分类号 H03L7/085
代理机构 代理人
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