发明名称 |
DECOMPRESSION PROCESSOR FOR VIDEO APPLICATION |
摘要 |
PURPOSE: To attain communication with an external dynamic RAM via a memory bus by decoding a compressed video signal and executing inverse discrete cosine transformation so as to make communication with a host computer via a host bus. CONSTITUTION: A processor 201 of a video uncompression circuit 200 reads/ writes a built-in data register and a control register to entirely control a decoder coprocessor 202, an inverse discrete cosine transformation coprocessor 203 and a motion compensation coprocessor 204 via a global bus 205 so as to attain intercommunication. Furthermore, communication is made with the host computer via the host bus 206 and with an external dynamic RAM via a memory bus 208. |
申请公布号 |
JPH07131785(A) |
申请公布日期 |
1995.05.19 |
申请号 |
JP19920055338 |
申请日期 |
1992.03.13 |
申请人 |
C KIYUUBU MAIKUROSHISUTEMUZU |
发明人 |
SUTEIIBUN SHII PAASERU;DEIBITSUDO II GARUBI;FURANKU EICHI RIYAO;IBONNU SHII TSUE |
分类号 |
G06T1/20;G06T9/00;G09G5/36;G09G5/39;G10L19/00;G10L19/02;H03M7/30;H03M7/42;H04N5/21;H04N5/44;H04N5/60;H04N5/907;H04N7/015;H04N7/26;H04N7/30;H04N7/50;H04N21/2368;H04N21/434;(IPC1-7):H04N7/30 |
主分类号 |
G06T1/20 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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