| 摘要 |
PURPOSE:To provide a memory cell structure of an SRAM which has small plane lay-out area and is suitable for high integration. CONSTITUTION:A pair of driver transistors Q1, Q2 and a pair of access transistors Q3, Q4 are formed in a memory cell region M.C. Each of the access transistors Q3, Q4 is comprised of a field effect transistor having gate electrode layers 15a, 15b. An insulation layer 29 is formed to have a contact hole which is formed on the driver transistors Q1, Q2 and the access transistors Q3, Q4 and reaches the gate electrode layers 15a, 15b within the memory cell region M.C. Each conductive layer is formed on an insulation layer to come into contact with the game electrode layers 15a, 15b through each contact hole. |
