发明名称 SATELLITE RECEIVER
摘要 PURPOSE:To improve the S/N by preparing a cut-off freqency setting means for specific frequency in a navigation data extracting circuit and providing a further lower frequency setting means in an information circuit for carrier frequency, phase and pseudo-distance. CONSTITUTION:The satellite receiver is constructed by 2-stage closed loop circuits that respectively consist of first and second Delay-Locked-Loop (DLL) parts 6 and 12 and first and second Phase-Locked-Loop (PLL) parts 7 and 13. In the first stage, a cut-off frequency in a range where a modulation frequency for navigation data of 50Hz can pass through, is set for only extracting the navigation data from the closed loop that is formed by the PLL on the first stage circuit. In the second stage, a cut-off frequency lower than that in the first stage is set so as to obtain a psendo distance information from a closed loop that is formed by the DLL on the second stage circuit and further to obtain a carrier frequency and phase from a closed loop that is formed by the PLL on the second stage circuit.
申请公布号 JPH07128431(A) 申请公布日期 1995.05.19
申请号 JP19930295963 申请日期 1993.11.02
申请人 JAPAN RADIO CO LTD 发明人 KAWASHIMA SHIGEO
分类号 G01C21/00;G01S19/24;G01S19/37;(IPC1-7):G01S5/14 主分类号 G01C21/00
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