发明名称 |
METHOD AND APPARATUS RELATED TO CACHE MEMORY |
摘要 |
A cache includes a cache array and a cache controller. The cache array has a plurality of entries. The cache controller is coupled to the cache array. The cache controller evicts entries from the cache array according to a cache replacement policy. The cache controller evicts a first cache line from the cache array by generating a writeback request for modified data from the first cache line, and subsequently generates a writeback request for modified data from a second cache line if the second cache line is about to satisfy the cache replacement policy and stores data from a common locality as the first cache line. |
申请公布号 |
US2015019823(A1) |
申请公布日期 |
2015.01.15 |
申请号 |
US201313942291 |
申请日期 |
2013.07.15 |
申请人 |
Advanced Micro Devices, Inc. |
发明人 |
Wang Zhe;Gu Junli;Xu Yi |
分类号 |
G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
|
代理人 |
|
主权项 |
1. A processor comprising:
a cache array having a plurality of entries; and a cache controller coupled to said cache array, said cache controller for evicting entries from said cache array according to a cache replacement policy, wherein said cache controller evicts a first cache line from said cache array by generating a writeback request for modified data from said first cache line, and subsequently generates a writeback request for modified data from a second cache line if said second cache line is about to satisfy said cache replacement policy and stores data from a common locality as said first cache line. |
地址 |
Sunnyvale CA US |