MONOLITHIC THREE DIMENSIONAL (3D) RANDOM ACCESS MEMORY (RAM) ARRAY ARCHITECTURE WITH BITCELL AND LOGIC PARTITIONING

摘要

A monolithic three dimensional (3D) memory cell array architecture with bitcell and logic partitioning is disclosed. A 3D integrated circuit (IC) (3DIC) is proposed which folds or otherwise stacks elements of the memory cells into different tiers within the 3DIC. Each tier of the 3DIC has memory cells as well as access logic including global block control logic therein. By positioning the access logic and global block control logic in each tier with the memory cells, the length of the bit and word lines for each memory call are shortened, allowing for reduced supply voltages as well as generally reducing the overall footprint of the memory device.

主权项

1. A three dimensional (3D) random access memory (RAM), comprising:
a first 3D integrated circuit (IC) (3DIC) tier, comprising:
a first RAM data bank disposed in the first 3DIC tier;a second RAM data bank disposed in the first 3DIC tier;a first RAM access logic comprising a first global block control logic disposed between the first RAM data bank disposed in the first 3DIC tier and the second RAM data bank disposed in the first 3DIC tier, the RAM access logic configured to control data access to the first RAM data bank disposed in the first 3DIC tier and the second RAM data bank disposed in the first 3DIC tier; a second 3DIC tier, comprising:
a first RAM data bank disposed in the second 3DIC tier;a second RAM data bank disposed in the second 3DIC tier;a second RAM access logic comprising a second global block control logic disposed between the first RAM data bank disposed in the second 3DIC tier and the second RAM data bank disposed in the second 3DIC tier, the second RAM access logic configured to control data access to the first RAM data bank disposed in the second 3DIC tier and the second RAM data bank disposed in the second 3DIC tier.