Redeposition Control in MRAM Fabrication Process

摘要

Methods and structures are described to reduce metallic redeposition material in the memory cells, such as MTJ cells, during pillar etching. One embodiment forms metal studs on top of the landing pads in a dielectric layer that otherwise covers the exposed metal surfaces on the wafer. Another embodiment patterns the MTJ and bottom electrode separately. The bottom electrode mask then covers metal under the bottom electrode. Another embodiment divides the pillar etching process into two phases. The first phase etches down to the lower magnetic layer, then the sidewalls of the barrier layer are covered with a dielectric material which is then vertically etched. The second phase of the etching then patterns the remaining layers. Another embodiment uses a hard mask above the top electrode to etch the MTJ pillar until near the end point of the bottom electrode, deposits a dielectric, then vertically etches the remaining bottom electrode.

主权项

1. An array of memory cells on a chip comprising:
a set of landing pads electrically connected to control circuitry for the array of memory cells; a set of metal studs disposed over the set of landing pads, with each metal stud disposed in electrical contact with one landing pad, each metal stud being embedded in a layer of dielectric material; and a set of multi-layered memory cell pillars each having a bottom electrode and being disposed over the set of metal studs with each metal stud electrically connecting a bottom electrode in a memory cell pillar to a landing pad.