Highly Integrated Scalable, Flexible DSP Megamodule Architecture

摘要

This invention addresses implements a range of interesting technologies into a single block. Each DSP CPU has a streaming engine. The streaming engines include: a SE to L2 interface that can request 512 bits/cycle from L2; a loose binding between SE and L2 interface, to allow a single stream to peak at 1024 bits/cycle; one-way coherence where the SE sees all earlier writes cached in system, but not writes that occur after stream opens; full protection against single-bit data errors within its internal storage via single-bit parity with semi-automatic restart on parity error.

主权项

1. A digital signal processor comprising:
a data register file including a plurality of data registers designed by register number storing data; an instruction memory storing instructions each specifying a data processing operation and at least one data operand by register number; an instruction decoder connected to said instruction memory for sequentially recalling instructions from said instruction memory and determining said specified data processing operation and said specified at least one operand; at least one operational unit connected to said data register file and said instruction decoder for performing data processing operations upon at least one operand corresponding to an instruction decoded by said instruction decoder and storing results in an instruction specified data register; a stream engine connected to said instruction decoder operable in response to a stream start instruction to recall from memory a stream of an instruction specified plurality of data elements; a stream head register connected to said stream engine and readable by said at least one operational unit as an operand, said stream head register storing a first fetched data element of said stream; and wherein said at least one operational unit is responsive to a stream operand instruction to receive at least one operand from said stream head register.