发明名称 FAULT BITS SCRAMBLING MEMORY AND METHOD THEREOF
摘要 A fault bits scrambling memory and method thereof relate to a memory including at least one memory bank. The memory bank includes a memory module, a scrambling-logic unit, a self-testing unit and a scrambling code generating unit. The memory module includes a plurality of pages. Each page has a plurality of memory cells, and each memory cell has a physical address. The scrambling logic unit receives a scrambling code and the physical address to generate a mapping address by logical calculation, and outputs the mapping address to the memory module. The self-testing unit detects the faulty memory cells of each page. The scrambling code generating unit is applied to generate the scrambling code to maintain the number of the faulty memory cells corresponding to the mapping address of the same page is up to a maximum tolerance.
申请公布号 US2015019924(A1) 申请公布日期 2015.01.15
申请号 US201414230554 申请日期 2014.03.31
申请人 NATIONAL TAIWAN UNIVERSITY OF SCIENCE AND TECHNOLOGY 发明人 LU Shyue-Kung;JHENG Hao-Cheng
分类号 G11C29/08 主分类号 G11C29/08
代理机构 代理人
主权项 1. A fault bits scrambling memory, comprising: at least a memory bank, each memory bank comprising a memory module, the memory module comprising a plurality of pages, each page comprising a plurality of memory cells, each memory cell having a physical address; a scrambling logic unit, receiving a scrambling code and the physical address to generate a mapping address by logical computation, and outputting the mapping address to the memory module so that an external module accesses the data of the memory cell corresponding to the mapping address according to the physical address; a self-testing unit, detecting faulty memory cells of each page to generate a faulty information; and a scrambling code generating unit, receiving the faulty information and generating the scrambling code to maintain the number of the faulty memory cells corresponding to the mapping address of the same page is up to a maximum tolerance.
地址 TAIPEI TW