Predication Methods for Vector Processors

摘要

A predication method for vector processors that minimizes the use of embedded predicate fields in most instructions by using separate condition code extensions. Dedicated predicate registers provide fine grain predication of vector instructions where each bit of a predicate register controls 8 bit of the vector data.

主权项

1. A branch predication system comprising:
a general purpose register file operable to store scalar or vector data; one or more predicate registers; a predication functional unit operable to independently manipulate predication bits and is coupled to the predicate registers; a compare functional unit operable to write into the predicate registers; one or more functional units coupled to the predication functional unit and to the predication registers.